High-Performance Cache Architecture Lead

1 week ago


Bengaluru, Karnataka, India Mulya Technologies Full time

At Mulya Technologies, we are seeking a seasoned expert to lead our cache architecture efforts in designing high-performance systems. As Cache Architecture Lead, you will play a pivotal role in shaping the future of processor L2 and LLC (Last Level Cache) design.

The ideal candidate will have at least 1 generation of processor L2 cache or LLC design delivery leadership experience and expertise in cache coherence protocols for symmetric multiprocessors (SMP). You should also be well-versed in NuCA / NuMA architectures and implementations, as well as memory consistency, store ordering, weakly and strongly ordered memory concepts.

Your primary responsibility will be to develop and architect L2 cache and LLC designs that meet capacity, latency, bandwidth, and RAS requirements. This includes presenting proposed architectures in high-level design discussions, developing micro-architecture, designing RTL, and collaborating with Verification, DFT, Physical design, FW, and SW teams to bring features to life.

You will also participate in silicon bring-up and validation of the hardware and lead a team of engineers, guiding and mentoring them to ensure project success. Additionally, you will estimate overall effort to develop features and silicon area and wire usage.

This is an exciting opportunity to join our team and contribute to cutting-edge cache architecture design. If you have 8 to 20 years of relevant experience and are passionate about delivering exceptional results, please apply.

Estimated salary: $250,000 - $350,000 per year.



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