Lead Verification Expert for Advanced SOC Designs
5 days ago
We are seeking a highly skilled Senior Staff Engineer to join our team at Cyient.
Location: Bangalore or Hyderabad, India
Estimated Salary: ₹ 30-80 Lacs per annum (dependent on experience)
Job Description:
We are looking for an experienced senior verification engineer with more than 5 years of experience in ASIC/SOC/IP/block level functional verification using system verilog/UVM.
The ideal candidate will have a strong command of UVM, advanced UVM and system verilog.
Main Responsibilities:
- Develop a comprehensive test plan, complete test-bench and robust verification environment including interface agents and scoreboard in UVM
- Possess deep knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB
- Strong debugging skills to address TB issues quickly and test failures
- Take responsibility for verification closure by addressing coverage and managing bug reports
- Proficiency in using industry standard verification tools such as Questa, VCS or ModelSim
- Experience with scripting languages like python, perl or TCL for automation tasks
- Manage a team of 6 to 7 Engineers, Interact with the customer on the tasks and status updates
- Experience working with Japan customer is a must
- Japan speaking is a mandatory skill
About the Role:
This is a great opportunity for a seasoned verification expert to take on a leadership role and drive the verification process for advanced SOC designs.
What We Offer:
- A competitive salary package
- A challenging and rewarding work environment
- Opportunities for career growth and development
- A collaborative and dynamic team
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