Verification Engineer for ASIC Design Flow
3 weeks ago
About eInfochips (An Arrow Company)
Job Opportunity for Verification Engineer
About the Role
With at least 4 years of experience in relevant fields, you will be responsible for expertise in ASIC verification methodologies and ASIC design flow. Working with SV and UVM methodology and knowledge of at least one industry-standard protocol like Ethernet, PCIe, MIPI, USB, AXI, RISC-V, AMBA, or DDR is required. You must have executed at least 2 SoC verification projects. Additionally, experience in UVM, formal verification, mixed-signal simulations, power-aware simulations, setting up and debugging functional and gate-level simulations, translating functional requirements into verification plans, developing verification environment and regression setup, and coverage analysis and closure is desired.
Requirements
Experience in ASIC design flow, SV and UVM methodology, and industry-standard protocols. Experience in executing SoC verification projects, UVM, formal verification, mixed-signal simulations, power-aware simulations, and setting up and debugging functional and gate-level simulations. Ability to translate functional requirements into verification plans and develop verification environment and regression setup.
What We Offer
eInfochips offers a dynamic work environment with opportunities for growth and development. If you are a detail-oriented and organized individual with a passion for verification engineering, we encourage you to apply.
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