Senior Physical Verification Engineer for Complex SoC Design
3 hours ago
About the Role
">This is a senior-level position for a physical verification engineer specializing in complex SOC/Cores/Blocks DRC, LVS, ERC, ESD, DFM, and Tapeout Work. The ideal candidate will work hands-on to solve critical design and execution issues related to physical verification and sign-off.
Responsibilities
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- Own physical verification and sign-off flows, methodologies, and execution of SoC/IP/Blocks">
- Expertise in physical verification of SoC/Full-chip-level and/or block-level DRC">
- Experience and understanding of all phases of the IC design process from RTL->GDS2 (LVS, ERC/PERC, DFM, OPC, Tapeout process)">
- Preferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at major foundries">
- Developing sign-off methodology/flow and supporting a larger team">
- Debugging LVS issues at chip-level with complex analog-mixed signal IPs">
- Design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)">
- Physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps, and other full-chip components">
- Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up, etc.">
- Experience with ERC rules, PERC rules, ESD rules has an added advantage">
- Expert in EDA Tools: Mentor (Calibre), Synopsys (ICV)/ Cadence (Pegasus)">
Requirements
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- Strong communication skills, problem-solving, and analytical skills">
- BTECH/MTECH with 5-15 years of experience">
What We Offer
">A competitive salary package with opportunities for career growth and development. Estimated annual salary: ₹45,00,000 - ₹80,00,000 (depending on location and experience).
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