Senior Analog ASIC Design Engineer
2 weeks ago
About Western Digital
Western Digital is a leader in data storage solutions, empowering people and businesses to unlock the full potential of their data. Our mission is to power global innovation and push the boundaries of technology to make what was once impossible, possible.
We are a company of problem solvers, passionate about creating innovative solutions that meet the evolving needs of our customers. With a rich history of innovation, we've been driving technological advancements for decades, from enabling systems to make cities safer and cars smarter, to powering the data centers behind many of the world's biggest companies and public cloud.
Our culture values diversity, equity, and inclusion, and we believe that the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us.
Job Overview
We're seeking an experienced Principal Engineer to lead the development of mixed signal CAD design flows. As a technical lead, you will be responsible for further developing concepts and methods for EDA design environments with a focus on analog/mixed signal ASIC design in advanced nodes.
This role requires a strong understanding of PDKs, effective management of PDK libraries, collaterals, and driving migration of design environments for incremental releases. You will also develop Calibre Physical Verification decks for CMOS PLANAR and FINFET technologies, including DRC, LVS, PERC, FILL LPE, and shape generation decks and scripts.
In addition to these responsibilities, you will contribute to the development and validation of PV tools and flows like parasitic extraction, EMIR drop, and substrate noise analysis. You will work closely with the IT team to fulfill advanced node-specific requests and collaborate with the CAD/IT team to ensure the operation and support of all ASIC designers worldwide.
Key Responsibilities
Develop and maintain high-quality analog/mixed signal CAD design flowsLead the development of Calibre Physical Verification decks for CMOS PLANAR and FINFET technologiesCollaborate with cross-functional teams to drive innovation and solve complex problemsContribute to the development and validation of PV tools and flowsMaintain a deep understanding of industry trends and emerging technologiesProvide technical guidance and mentorship to junior engineersQualifications
To succeed in this role, you should have a University degree (Master/PhD) in Electrical Engineering or a comparable subject. You should also possess a minimum of 10+ years of development experience in mixed signal CAD design flows, with expertise in state-of-the-art design tools (EDA-vendors Cadence, Synopsys, Mentor) and software development methodologies and tools.
You should be fluent in English and German written and spoken, and possess excellent communication and problem-solving skills. Experience with Cadence custom IC Virtuoso platform and physical verification tools for DRC, LVS, and parasitic extraction is highly desirable.
What We Offer
We offer a competitive salary of $180,000 per year, comprehensive benefits package, and opportunities for professional growth and development. If you're passionate about innovation, collaboration, and pushing the boundaries of technology, we encourage you to apply.
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