Silicon Layout Optimization Specialist

2 weeks ago


Bengaluru, Karnataka, India Modernize Chip Solutions (MCS) Full time
About Modernize Chip Solutions

Modernize Chip Solutions (MCS) is a leading provider of innovative semiconductor solutions.

Job Summary

We are seeking an experienced Physical Verification Engineer to join our team in Bangalore. The successful candidate will be responsible for ensuring the physical layout of our IC designs accurately matches the schematic and adheres to electrical constraints.

Responsibilities
  • Design Rule Checking (DRC): Perform DRC checks using industry-standard tools to identify violations of manufacturing design rules, collaborating with layout designers to resolve issues.
  • Layout vs. Schematic (LVS) Verification: Conduct LVS checks to verify the physical layout accurately matches the schematic and ensure there are no electrical connectivity discrepancies.
  • Electrical Rule Checking (ERC): Verify that the layout adheres to electrical constraints and requirements, such as voltage and current limitations, ensuring the IC functions as intended.
  • Design for Manufacturing (DFM): Collaborate with design and manufacturing teams to optimize the layout for the semiconductor fabrication process, addressing lithography and process variation concerns.

This role requires 5+ years of experience in a related field and strong expertise in silicon layout optimization. If you have a passion for innovation and excellence, we encourage you to apply.

Estimated Salary: ₹1,200,000 - ₹1,500,000 per annum based on location and experience.



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