Highly Skilled ASIC Design Engineer

3 weeks ago


Bengaluru, Karnataka, India Cisco Full time

Work with Our Expert Team

Our talented Physical Design team in Bangalore, India is seeking a highly skilled ASIC Design Engineer to join our ranks. As a member of this team, you will be involved in creating next-generation state-of-the-art networking chips in advanced process nodes.

Your Key Responsibilities

  1. Analyze current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to existing physical design related Tools, Flow and Methodology.
  2. Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies.
  3. Good understanding of different CTS strategies and provide feedback to Implementation Team.
  4. As a member of the physical design team, drive methodologies and 'best known methods' to streamline and automate physical design work.
  5. STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs.
  6. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows.
  7. Work on Automation scripts within STA tools for Methodology development. Excellent debugging skills in implementation issues and ability to produce creative solutions.
  8. Evaluate multiple timing methodologies/tools on different designs and technology nodes.
  9. Good scripting skills (TCL/SHELL/PERL/Python) is a MUST.

Your Qualifications

  1. All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.
  2. Hierarchical design implementation approach, Timing closure, physical convergence.
  3. Power Integrity Analysis.
  4. Experience with large designs (> 100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies.
  5. Familiarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies.

You should also have hands on experience with the following Tool sets

  1. Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2.
  2. Synthesis Tools: Synopsys DC/FC.
  3. Formal Verification : Synopsys Formality and Cadence LEC.
  4. Static Timing verification: Primetime-DMSA.
  5. Power Integrity : Apache Redhawk.
  6. Physical Design Verification Synopsys ICV, Mentor Calibre.
  7. Scripting: TCL, Perl is required; Python is a plus.

Bachelor's degree in Telecommunications Engineering, Computer Science, MIS, or related experience.



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