High-Performance SoC Architect
8 hours ago
Company Overview
MIPS is a pioneering company in the field of RISC-based computing, having introduced the first MIPS RISC architecture over 30 years ago. Today, we are leading a RISC revolution by accelerating the RISC-V architecture for high-performance applications. Our eVocore processors provide a new level of scalability for heterogeneous computing.
About This Role
We are seeking an experienced Sr. Staff Design Engineer to lead the development of high-performance SoCs. The ideal candidate will have a strong background in microcontroller or processor architectures and experience with simulators and waveform debugging tools. Additionally, they should have knowledge of logic design principles, timing, and power implications.
Key Responsibilities
- Develop high-performance microarchitectures and designs for multiple blocks of SoCs or control IPs.
- Perform early architectural exploration, research, and detailed specification development.
- Configure design features, assess, and refine RTL design to target power, performance, area, and timing goals.
- Support functional verification and assist in the design verification strategy.
- Partner with engineering teams to implement and validate physical design aspects of timing, area, reliability, testability, and power.
Qualifications
- Hands-on experience with high-performance microcontroller or microprocessor architectures.
- Familiarity with simulators and waveform debugging tools.
- Knowledge of logic design principles, timing, and power implications.
- Understanding of System Verilog, UVM, UPF, and parametrized designs.
- Experience with EDA tool vendors like Synopsys, Cadence, and Tessent.
- In-depth knowledge of bus architectures like AXI, AHB, and peripherals.
- Excellent analytical and problem-solving skills.
- Bachelor's or Master's degree with 5-10 years of experience or PhD with 5+ years of work experience.
Salary: $140,000 - $200,000 per year
Location: Flexible remote work options available. We prioritize talent over location.
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