Senior System-on-Chip Integration Lead

17 hours ago


Delhi, Delhi, India Texas Instruments Full time
Job Description

We are seeking a highly experienced Senior System-on-Chip Integration Lead to join our team at Texas Instruments. In this role, you will be responsible for leading the integration of complex multi-processor ARM architecture based SoCs.

About the Role

The successful candidate will have 5-12 years of experience in IP/SoC/subsystem design/integration and will be responsible for managing a high impact FE team, collaborating with systems, IP, and DV teams, and ensuring timely SoC integration releases that cater to Product Requirements.

Key Responsibilities
  • Lead a SoC FE team to own SoC integration of a complex multi-processor ARM architecture based SoC up to RTM
  • Manage a high impact FE team and take accountability for their timely deliverables
  • Collaborate with systems, IP, and DV teams to align on feature updates, bug fixes, IP deliverables, and ensure timely SoC integration releases that cater to Product Requirements
  • Interact and engage early-on with SoC system architect and ensure performance analysis, functional safety requirements, system level use-cases, and pin mixing is fully comprehended
  • Own SoC level Component -> Debug SS, System clock reset, and PM Micro architecture and SC Integration and work closely with architecture team for microarchitecture aspects of the same
  • Own Chip top creation, Hard macro integration, Pin mux Implementations and work closely with architecture team for microarchitecture details of
  • Work with backend, DFT team, flow teams to come up with initial SoC release
  • Responsible for RTL releases, Frontend checks for each compile
  • Point of contact person to IP team from SoC perspective, key member to drive integration reviews and participate in DV reviews to give feedback
  • Drive complete SoC integration, LEC, LINT checks, and CDC/RDC analysis to ensure high-quality deliverables
  • Responsible for ensuring power intent of the SoC is understood and implemented correctly through Low-Power checks like CLP
Requirements
  • Educational requirement: Bachelor or Masters in EE/ECE/CS or related specializations
  • Experience with integration of SoC's with ARM processors, complex bus architectures
  • Well-experienced with analysis and understanding of system level use-case scenarios, safety requirements, etc
  • Experience with SoC power analysis and power optimization through innovative schemes
  • Strong experience with advanced low-power techniques and tools such as UPF/CPF, CLP
  • Good understanding of constraints development for Physical Design implementation / Static Timing Analysis
  • Experience with industry standard FrontEnd tools like JasperGold, SpyGlass, LEC, etc
  • Well-experienced with EDA tools such as VCS/Questa/Incisive simulators, Debug tools, and Formal verification tools
  • Good understanding of SoC Debug architectures, Design-for-Debug, Design-for-Test will be highly desirable
  • Strong written and verbal communication skill with the ability to explain and present complex ideas
  • Passionate about mentoring and developing people in their careers
Compensation

The estimated salary for this role is $140,000-$200,000 per year, depending on experience and qualifications.



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