Senior ASIC Design Verification Engineer
2 weeks ago
About the Role:
Cientra Techsolutions is seeking a highly skilled and experienced ASIC design verification engineer to join our team. This role involves developing modules for next-generation ASICs used in radio equipment and Radio Access Network compute.
Key responsibilities include:
- Designing and verifying complex digital circuits
- Developing UVM test cases and environments
- Collaborating with cross-functional teams to ensure seamless integration
- Producing high-quality product documentation
Requirements:
- Minimum 3-10 years of experience in ASIC/RTL design verification
- Strong knowledge of SystemVerilog and UVM
- Excellent problem-solving skills and attention to detail
- Ability to work in a fast-paced environment and meet deadlines
What We Offer:
- A competitive salary: $120,000 - $180,000 per year
- Ongoing professional development opportunities
- A collaborative and dynamic work environment
How to Apply:
We are an equal opportunities employer. Please submit your application, including your resume and a cover letter, to apply for this exciting opportunity.
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