Senior Physical Design Engineer
7 days ago
About ACL Digital
Job Description:
We are looking for a seasoned Senior Physical Design Engineer to join our team in Bangalore. As a key member of our design group, you will be responsible for the independent planning and execution of all aspects of physical design, including floor planning, place and route, clock tree synthesis, extraction, timing closure, power and signal integrity analysis, and physical verification.
The ideal candidate should have a deep understanding of concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure. You must have participated in all stages of the design process, including floor planning, placement, CTS, routing, physical verification, and IREM. Experience with timing closure methodologies and good understanding of DRC, LVS, ERC, and PERC rule files for lower tech node layout verification is essential.
You will also be required to work on lower tech node designs with good automation skills in Perl, TCL, and EDA tool-specific scripting. Additionally, you will need to take complete ownership of blocks/sub-systems for the complete execution cycle, demonstrating out-of-the-box thinking to meet tighter PPA requirements.
About the Role:
- Plan and execute all aspects of physical design, including floor planning, place and route, clock tree synthesis, extraction, timing closure, power and signal integrity analysis, and physical verification.
- Collaborate with cross-functional teams to deliver high-quality designs that meet technical specifications and performance requirements.
- Develop and maintain knowledge of emerging technologies, tools, and methodologies to stay ahead in the field.
Requirements:
- 5+ years of experience in physical design engineering, preferably in the semiconductor industry.
- Deep understanding of concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure.
- Experience with timing closure methodologies and good understanding of DRC, LVS, ERC, and PERC rule files for lower tech node layout verification.
- Excellent problem-solving skills, with ability to work independently and as part of a team.
- Good communication and collaboration skills, with ability to work effectively with cross-functional teams.
- Ability to adapt to changing priorities and deadlines, with a focus on delivering high-quality results.
What We Offer:
- A competitive salary range of ₹25-35 lakhs per annum, depending on experience.
- A comprehensive benefits package, including health insurance, retirement plan, and paid time off.
- Opportunities for career growth and professional development, with access to training programs and mentorship.
- A dynamic and collaborative work environment, with a focus on innovation and excellence.
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