Verification Environment Specialist

17 hours ago


bangalore, India beBeeVerification Full time

Job Role OverviewWe are seeking an experienced professional to develop and maintain verification environments for block-level and IP-level designs, leveraging expertise in System Verilog/UVM.Responsibilities:- Develop and maintain high-quality verification components using SystemVerilog/UVM.- Create and execute comprehensive verification plans (VPlans) to drive coverage closure.- Implement and verify designs using real number modeling (RNM) for mixed-signal interfaces.- Perform netlist and gate-level simulations (GLS) to validate post-synthesis and post-layout functionality.- Debug functional and testbench issues to ensure high-quality reusable verification components.Requirements and QualificationsExperience: 5-10 years of experience in functional verification with System Verilog/UVM.Key Skills:* Strong expertise in System Verilog/UVM programming language.* Experience with block/IP-level verification methodologies.* Strong communication skills and ability to work independently.



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