UST | ASIC Desing Verification Lead | bangalore

Hi All, We are looking for ASIC design verification lead with UVM and Verilog experience. from 8 to 16 years Please forward your resume to Regards, Jaya

Hi All, We are looking for ASIC design verification lead with UVM and Verilog experience. from 8 to 16 years Please forward your resume to Regards, Jaya

Hi All, We are looking for ASIC design verification lead with UVM and Verilog experience. from 8 to 16 years Please forward your resume to Regards, Jaya

Hi All,We are looking for ASIC design verification lead with UVM and Verilog experience.from 8 to 16 years Please forward your resume to jayalakshmi.r2@ust.comRegards,Jaya

The certified Workday Data Conversion Lead will be responsible for data conversion and tenant build activities on deployment projects. Hands-on Workday data conversion experience, good communication, responsiveness, ability to manage multiple tasks and consulting on data conversion/ETL approaches are key attributes for this role. The Opportunity and...

The certified Workday Data Conversion Lead will be responsible for data conversion and tenant build activities on deployment projects. Hands-on Workday data conversion experience, good communication, responsiveness, ability to manage multiple tasks and consulting on data conversion/ETL approaches are key attributes for this role. The Opportunity and...

Hi , Greetings ....!!!! We are hiring for an DV Engineer for one of our reputed client. Role: DV Engineer Location: Malaysia /Bangalore Experience _5-8 years Skills Job Description: - Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. - Experience and knowledge in Verification of...

Hi , Greetings ....!!!! We are hiring for an DV Engineer for one of our reputed client. Role: DV Engineer Location: Malaysia /Bangalore Experience _5-8 years Skills Job Description: Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Experience and knowledge in Verification of IP’s...

Who we are: Born digital, UST transforms lives through the power of technology. We walk alongside our clients and partners, embedding innovation and agility into everything they do. We help them create transformative experiences and human-centered solutions for a better world. UST is a mission-driven group of over 39,000+ practical problem solvers and...

Hi ,Greetings ....!!!!We are hiring for an DV Engineer for one of our reputed client.Role: DV EngineerLocation: Malaysia /BangaloreExperience _5-8 yearsSkillsJob Description:- Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM.- Experience and knowledge in Verification of IP’s related to...

Hi ,Greetings ....!!!!We are hiring for an DV Engineer for one of our reputed client.Role: DV EngineerLocation: Malaysia /BangaloreExperience _5-8 yearsSkillsJob Description:Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM.Experience and knowledge in Verification of IP’s related to...

Hi , Greetings ....!!!! We are hiring for an DV Engineer for one of our reputed client. Role: DV Engineer Location: Malaysia /Bangalore Experience _5-8 years Skills Job Description: - Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. - Experience and knowledge in Verification...

Who we are:Born digital, UST transforms lives through the power of technology. We walk alongside our clients and partners, embedding innovation and agility into everything they do. We help them create transformative experiences and human-centered solutions for a better world.UST is a mission-driven group of over 39,000+ practical problem solvers and creative...

Hi ,Greetings ....!!!!We are hiring for an DV Engineer for one of our reputed client.Role: DV EngineerLocation: Malaysia /BangaloreExperience _5-8 years SkillsJob Description:Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM.Experience and knowledge in Verification of IP’s related to...

Hi , Greetings ....!!!! We are hiring for an DV Engineer for one of our reputed client. Role: DV Engineer Location: Malaysia /Bangalore Experience _5-8 years Skills Job Description: Good understanding of ASIC verification concepts and techniques. Very good knowledge of Verilog/System Verilog and UVM. Experience and knowledge in Verification of IP’s...

Hi All, We are looking for 2 profiles with 6-10 years experienced in DFx verification . The job description is good experience in RTL verification and debug, GLS simulations and debug, Verilog coding experience, good understanding on JTAG and verification in Testmode. Its good to have pattern generation and Silicon debug experience. Please forward your...

Hi All, We are looking for 2 profiles with 6-10 years experienced in DFx verification . The job description is good experience in RTL verification and debug, GLS simulations and debug, Verilog coding experience, good understanding on JTAG and verification in Testmode. Its good to have pattern generation and Silicon debug experience. Please forward your...

Hi All,We are looking for 2 profiles with 6-10 years experienced in DFx verification.The job description is good experience in RTL verification and debug, GLS simulations and debug, Verilog coding experience, good understanding on JTAG and verification in Testmode. Its good to have pattern generation and Silicon debug experience.Please forward your resume to...

Hi All, We are looking for 2 profiles with 6-10 years experienced in DFx verification . The job description is good experience in RTL verification and debug, GLS simulations and debug, Verilog coding experience, good understanding on JTAG and verification in Testmode. Its good to have pattern generation and Silicon debug experience. Please forward your...

ASIC Engineer - DV Job Description 4 to 8yrs of experience in Design verification Developed verification methodology and testplan for new design Good knowledge on the verification flows, SV and UVM Perform RTL code coverage and functional coverage, formal analysis Be responsible for defining the verification strategy and plan for the development ...