DFT Expert

Senior DFT StrategistWe are seeking a highly motivated and experienced Senior DFT Strategist to lead the development and implementation of comprehensive DFT strategies, including scan insertion, ATPG, and boundary scan techniques.The ideal candidate will have a strong understanding of DFT methodologies and be able to independently implement and optimize DFT strategies in complex ASICs and SoCs.Collaborate with cross-functional teams throughout the design flow to integrate DFT techniquesDevelop and implement strategic DFT plans, focusing on testability and manufacturabilityUtilize advanced DFT tools and methodologies to achieve high test coverage and fault detection ratesAnalyze test results, identify potential design issues, and provide recommendations for corrective actionsQualifications:Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)6-25 years of experience in Design for Testability (DFT) for ASICs or SoCsIn-depth knowledge of DFT concepts (scan insertion, ATPG, BSCAN, fault modeling, test coverage analysis)