ASIC Design Engineering Manager
1 week ago
Job Description:We are seeking an experienced ASIC Physical Design Lead with a strong background in timing closure and full-chip physical design to lead the development of complex ASIC projects from Netlist to GDSII.The ideal candidate will have expertise in synthesis, place and route, and static timing analysis as well as oversee full-chip physical design processes including floor planning, power grid design, clock tree synthesis, and signal integrity analysis.Develop and implement efficient physical design methodologies for complex ASIC projects.Lead a team of engineers to achieve timely project completion and high-quality results.Mentor junior engineers and provide guidance on best practices and industry standards.Required Skills and Qualifications:The successful candidate will possess:Strong technical knowledge of ASIC physical design, timing closure, and full-chip physical design.Experience with EDA tools and design automation software.Excellent communication and leadership skills.Benefits:This is a unique opportunity to work with a talented team of engineers and contribute to the development of cutting-edge technology. The company offers a competitive salary and benefits package, opportunities for professional growth and development, and a dynamic work environment.Others:We are committed to diversity and inclusion in the workplace and strive to create an environment where everyone feels valued and respected. We offer flexible working arrangements, professional training and development opportunities, and a comprehensive employee assistance program.
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ASIC Physical Design Engineer
6 days ago
Hyderabad, Telangana, India KriSemi Design Technologies LLC Full time ₹ 6,00,000 - ₹ 12,00,000 per yearCompany DescriptionKriSemi Design Technologies LLC is a leading service provider to semiconductor and EDA companies, specializing in Physical Design, Physical Verification, Analog and Mixed Signal Design, and Embedded Systems. Our passionate and dedicated professionals have deep insight into VLSI challenges and focus on trending technologies with a vision...
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Senior ASIC RTL Designer
2 weeks ago
hyderabad, India Eximietas Design Full timePosition: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...
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Senior ASIC RTL Designer
2 weeks ago
Hyderabad, India Eximietas Design Full timePosition: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...
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Senior ASIC RTL Designer
2 weeks ago
Hyderabad, India Eximietas Design Full timePosition: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...
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Senior ASIC RTL Designer
2 weeks ago
Hyderabad, India Eximietas Design Full timePosition: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ yearsDesign and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks.Create micro-architecture specs and ensure designs meet performance, power, and area targets.Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...
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Senior ASIC RTL Designer
2 weeks ago
Hyderabad, India Eximietas Design Full timePosition: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years - Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. - Create micro-architecture specs and ensure designs meet performance, power, and area targets. - Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA,...
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Senior ASIC RTL Designer
2 weeks ago
Hyderabad, India Eximietas Design Full timePosition: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...
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Senior ASIC RTL Designer
2 weeks ago
Hyderabad, India Eximietas Design Full timePosition: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...
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Senior ASIC RTL Designer
2 weeks ago
Hyderabad, India Eximietas Design Full timePosition: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...
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Senior ASIC RTL Designer
1 week ago
hyderabad, India Eximietas Design Full timePosition: ASIC RTL Design Engineer Location: Bangalore / Hyderabad Experience: 6+ years Design and develop synthesizable RTL using Verilog/SystemVerilog for complex ASIC/SoC blocks. Create micro-architecture specs and ensure designs meet performance, power, and area targets. Own RTL implementation, lint/CDC cleanup, and contribute to synthesis, STA, and DFT...
