UST | SoC design verification engineer | bangalore

2 weeks ago


bangalore, India UST Full time

Hi All,


Looking for Design Verification Engineer with UVM and Verilog experience.


Please forward your resume to jayalakshmi.r2@ust.com


Regards,

Jaya



  • bangalore, India UST Full time

    Hi All, Looking for Design Verification Engineer with UVM and Verilog experience. Please forward your resume to Regards, Jaya


  • bangalore, India UST Full time

    Hi All, Looking for Design Verification Engineer with UVM and Verilog experience. Please forward your resume to Regards, Jaya


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