High Performance System Designer

5 days ago

hyderabad, India beBeeEngineering Full time

Senior RTL Design Engineer for High-Performance SystemsWe are seeking an experienced RTL design engineer to lead the development of high-performance systems.Design and develop IP blocks for ARM Neoverse SoCs, integrating CMN fabric (e.g., CMN-700/S3) for cache coherence and interconnect.Develop Verilog/SystemVerilog RTL for high-performance, low-latency designs, leveraging industry-leading tools and methodologies.Configure CMN topologies using Arm Socrates for optimized performance and scalability, ensuring seamless integration with existing infrastructure.Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects, driving innovation in system-level design.Optimize designs for bandwidth, latency, and power in AI/HPC workloads, pushing the boundaries of what is possible in high-performance computing.The ideal candidate will possess a strong background in Verilog/SystemVerilog RTL design, deep knowledge of ARM Neoverse and CMN interconnects, and experience with Arm Socrates for CMN configuration. Additionally, they should be proficient in AMBA CHI, CXL, PCIe, or CCIX protocols, and have expertise with synthesis and timing tools (e.g., Synopsys Design Compiler).Key Responsibilities:Lead the development of high-performance systems, collaborating with cross-functional teams to drive innovation and excellence.Design and develop IP blocks for ARM Neoverse SoCs, ensuring seamless integration with existing infrastructure.Configure CMN topologies using Arm Socrates, optimizing performance and scalability.Implement protocols like AMBA CHI, ACE, CXL, PCIe for coherent interconnects, driving innovation in system-level design.Requirements:Strong background in Verilog/SystemVerilog RTL design.Deep knowledge of ARM Neoverse and CMN interconnects.Experience with Arm Socrates for CMN configuration.Proficiency in AMBA CHI, CXL, PCIe, or CCIX protocols.Expertise with synthesis and timing tools (e.g., Synopsys Design Compiler).

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