SOC Physical design
7 days ago
Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. SOC PD - Front End Integration (FEINT) Lead The Role The scoping of SOC PD FEINT (Front End Integration) lead includes Synthesis, Logic Equivalence, low power check, Timing Closure and full-chip SDC (constraints) generation. AMD design is big and complex with advanced process and technology. FEINT lead needs to have rich experience in each domain, control execution risk and lead the team to do high quality release on schedule. The lead needs to co-work with IP/DFT/PD teams, highlights critical issues and makes decisions to make project execution smoothly. The Person - 10-15 years working experience on ASIC Implementation - Knowledgeable in all aspects of ASIC design flow - Familiar with FEINT EDA tools - Good leadership skills - Good teamwork and script skills - Good training skills to ramp-up new team members Key Responsibilities - Own full-chip / sub-system / partition level Synthesis, Equivalence checking and low power checks/signoff - Co-work with IP/DFT/PD team to improve timing/area/power during synthesize - Netlist quality check including EQV/LowPower/Timing - Generate full-chip level SDC and SDC quality check - Do working assignment for team members, tracking and supporting for critical problems - Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective. - Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects. - Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology. Preferred Experience - Synthesize experience by Fusion-Compiler - EQV debug experience by FM/LEC - Low power check experience by VC-LP - Static Timing Analysis experience by PT - Experience in STA, constraints, timing signoff and physical design - Power Analysis experience by PTPX - Good at scripts, like Python/perl/Tcl/Shell - Excellent presentation and inter-communication skills. Academic Credentials Bachelor's or Master's in Electronics/Electrical/Computer Engineering Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.
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SOC Physical Design
1 day ago
Bengaluru, Karnataka, India Rivos Full time ₹ 1,00,00,000 - ₹ 2,00,00,000 per yearPositions are open for full-time SOC physical implementation from unit level to chip level, involving all aspects of physical design functions such as P&R, timing, floorplan, clocking, electrical analysis, and power. ResponsibilitiesOwn block level design from RTL-to-GDSII and drive synthesis, floor-planning, place & route, timing closure, and signoff.Work...
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SoC Physical Design Engineer
1 week ago
Bengaluru, Hyderabad, Noida, India Team Computers Full time ₹ 20,00,000 - ₹ 25,00,000 per yearLead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries.Excellent hands-on P&R skills with expert knowledge in ICC/InnovusExpert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and...
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SOC Physical design
3 days ago
Bengaluru, Karnataka, India AMD Full time ₹ 25,00,000 - ₹ 50,00,000 per yearWHAT YOU DO AT AMD CHANGES EVERYTHINGAt AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create...
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SOC Physical Design Engineer Lead
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Bengaluru, Karnataka, India Intel Full time ₹ 12,00,000 - ₹ 36,00,000 per yearPerforms physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing.Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.Conducts...
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CPU Physical Design Engineer
5 days ago
Bengaluru, India 7Rays Semiconductors Full timeJob Description Title : CPU Physical Design Lead Exp- 10+ Years - High speed core development Synth, constraints, and Physical Design - Engineer must have significant knowledge on highspeed cores including CPU, GPU, DDR etc - Must have synthesis & Constraints experience with PPA in mind - Must work with RTL designers for optimizations and feedback - Must be...
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Physical Design Manager
4 weeks ago
India Mulya Technologies Full timewww.sevyamultimedia.com Hyderabad About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. Chip Design Services Analog IP Design Foundation - OpAmp, Bandgap IOs - GPIO, I2C, LVDS Clocking - PLL Power - LDO SoC Design RTL...
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Bengaluru, India BITSILICA Full timeJob Description Key Responsibilities - Lead SoC/IP physical implementation through all stages of the RTL-to-GDSII flow for advanced nodes (7nm and below). - Drive PPA (Power, Performance, Area) optimization at block and top levels. - Own floorplanning, placement, CTS, routing, and signoff activities to meet design targets. - Perform STA, IR/EM analysis, and...
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ASIC SOC RTL Design Lead
3 weeks ago
Bengaluru, India Eximietas Design Full timeHi All,Greetings' from Eximietas Design....!We are Hiring ASIC SOC RTL Design Engineer/Leads.Job Title: ASIC SOC RTL Design Engineer/Leads..!Experience: 8+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:Eximietas Design is seeking an experienced and highly skilled ASIC...
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ASIC SOC RTL Design Lead
3 weeks ago
Bengaluru, India Eximietas Design Full timeHi All,Greetings' from Eximietas Design....!We are Hiring ASIC SOC RTL Design Engineer/Leads.Job Title: ASIC SOC RTL Design Engineer/Leads..!Experience: 8+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:Eximietas Design is seeking an experienced and highly skilled ASIC...
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ASIC SOC RTL Design Lead
3 weeks ago
Bengaluru, India Eximietas Design Full timeHi All,Greetings' from Eximietas Design....!We are Hiring ASIC SOC RTL Design Engineer/Leads.Job Title: ASIC SOC RTL Design Engineer/Leads..!Experience: 8+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:Eximietas Design is seeking an experienced and highly skilled ASIC...
