SignOff Semiconductors | Memory Layout Engineer | india
3 weeks ago
Job Description:
- Good understanding of basic VLSI concepts: CMOS, IC Fabrication, FINFET, RC Network etc.
- Experience with developing tight pitched memory (SRAM & MRAM etc) array layout with hierarchy layouts of Row decoders, Write drivers, Assist circuits, Sense Amplifiers, Memory Control circuit
- Collaborate with circuit designers to meet design specifications including physical/reliability verification checks.
- Proficiency with industry-standard EDA tools (e.g., Virtuoso, Custom Compiler, Calibre, ICV etc).
- Good Understanding of layout effects with related constraints in speed, parasitic, area, power and other second order effects.
- Strong problem-solving and communication skills, with the ability to work independently or as part of a team.
- Flexible to work in client location and ODC.
- Flexible to work in a cross-site team environment in different time zones.
- Figure out and create solutions to different problems.
- Independently work to determine methods and procedures on new technologies to mentor, co-ordinate activities of others as Team Lead. Good at documenting and presenting.
Requirements
Education
BE/B.Tech in ECE/EEE or M.Tech VLSI
Experience
4 - 8 Years
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