Principal SystemC Modeling and Simulation Engineer
4 weeks ago
Principal / Senior Staff SystemC Modeling and Simulation Engineer
Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad
A US based well-funded product-based startup looking for Highly talented Engineers for the following roles.
We are looking for a SystemC Modeling and Simulation Engineer
Responsibilities:
- System Level Modelling for Architecture exploration, Performance exploration, SoC performance analysis, trade-offs analysis
- SystemC model development for various abstractions ranging from Loosely Timed, Cycle Approximate to Cycle Accurate abstraction levels
- Models for architectural components like Memory subsystem, Bus Interconnect, Peripheral models, multi-core SoC platforms using SystemC, TLM
- Performance analysis of developed models using SPEC-HPC, SPEC-CPU benchmarks etc.
- Design and develop design algorithms in C/C++/SystemC for efficient HW implementation
Key Qualifications:
- 10+ years' experience in performance modelling using SystemC, TLM2.0, Extending TLM2.0
- Proficiency in C , OOPS, STL, data structures, algorithms, and programming concepts
- Exposure to any HDL: SystemC, Verilog, System Verilog
- Understanding of Microprocessor, Microcontrollers, SOC architecture, bus protocols etc.
- Familiarity with industry standard benchmarks such us SPEC-HPC, LLAMA, SPEC-CPU etc
- Familiarity with Memory architectures, Memory Controller architectures, Cache, MMU
- Knowledge of system bus (AMBA, OCP, NoC) and memory protocols (LPDDR5/LPDDR6/HBM4)
Contact:
Uday
Mulya Technologies
"Mining The Knowledge Community"
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