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Wafer Space

2 months ago

Bangalore, India Wafer Space - An ACL Digital Company Full time

Job Description :

- Good knowledge of Memory Controller & PHY, LPDDR5/DDR4/5 Protocols is preferred.

- Proven track record of building Testplan, UVM Environment from Scratch.

- Experience with Debugging, Scoreboard/Assertions development and Code Coverage Analysis.

- Sound knowledge of System Verilog and UVM Methodology.

- The position requires good Written & Verbal Communication Skills.

- Strong Commitment and ability to work in Cross Functional & Globally Dispersed Teams.

Experience Required : 5+ Years.

We are seeking a highly motivated and experienced Senior Design Verification Engineer to join our team.


In this role, you will be responsible for ensuring the functionality and performance of memory controller and interface designs, focusing on LPDDR5/DDR4/DDR5 protocols.


You will play a key role in developing and executing verification plans, building robust UVM environments, and collaborating with cross-functional teams to deliver high-quality designs.


Responsibilities :


- Develop comprehensive verification plans for memory controller and PHY designs


- Design and implement UVM testbenches from scratch, including drivers, monitors, scoreboards, and sequences


- Write and maintain System Verilog code for testbenches, assertions, and scoreboards


- Utilize advanced verification methodologies, including constrained random verification and coverage-driven verification


- Perform comprehensive debugging of verification environments and design issues


- Analyze code coverage and identify areas for improvement


- Collaborate with design engineers, architects, and other verification engineers to ensure successful design verification


- Document verification plans, testbenches, and results clearly and concisely


- Stay current with the latest memory protocols and verification methodologies


Qualifications :


- Master's degree (M.S./M.Tech) or Bachelor's degree (B.E./B.Sc.) in Electronics Engineering or a related field


- 5+ years of experience in design verification, with a focus on memory controller and PHY interfaces


- Proven track record of building robust UVM environments from scratch


- Expertise in System Verilog and UVM methodology


- Strong knowledge of LPDDR5/DDR4/DDR5 memory protocols (preferred)


- Experience with debugging techniques, scoreboard/assertion development, and code coverage analysis


- Excellent written and verbal communication skills


- Ability to work effectively in a cross-functional and globally dispersed team environment


- Strong commitment to quality and delivering on deadlines

(ref:hirist.tech)