Physical Design Engineer

2 days ago


New Delhi, India LeadSoc Technologies Pvt Ltd Full time

Job Description – Physical Design Engineer / Sr. Physical Design EngineerPosition:Physical Design Engineer / Sr. PD Engineer Location:Bengaluru /Hyderabad Experience:3–10 Year Company:LeadSoc Technologies Pvt LtdRole Overview: We are looking for a highly skilledPhysical Design Engineerto work on complex SoC and block-level implementation fromNetlist-to-GDSII. The ideal candidate should have strong hands-on experience inPnR tools,timing closure,low-power methodologies, andsign-off flows, along with strong problem-solving and communication skills.Key Responsibilities: Work onBlock/SOC level Physical Designfrom RTL to GDSII. Execute completePD implementation flowincluding floorplanning, power planning, placement, CTS, routing, extraction, and timing closure. Handlelow-power design methodologiesincluding UPF/CPF, power domains, isolation, retention cells, etc. Performcongestion analysis, timing analysis, and deliver improvedQoRacross design stages. Runphysical verificationand sign-off checks: STA DRC/LVS/Antenna ERC IR/EM analysis LEC Power analysis PerformECO implementation(timing and functional). Collaborate with RTL, DFT, architecture, and sign-off teams to ensure design convergence. Drive block-level and top-level closure with strong ownership and leadership. Utilize scripting (Perl/TCL) for flow automation and efficiency improvements. Ensure all deliverables meet schedule, quality, and performance targets.Required Skills & Experience: Strong experience inNetlist-to-GDSII / Physical Design / PnR / APR flows. Hands-on knowledge of: Synopsys ICC2, Fusion Compiler, Cadence Innovus, Tempus, Voltus In-depth understanding of PD stages:Floorplan, Placement, CTS, Routing, Extraction, Sign-off. Solid understanding oftiming, congestion, SI, IR/EM, and closure methodologies. Experience inECO (timing and functional)implementation. StrongPerl/TCL scriptingskills for automation. Good leadership, communication, and problem-solving skills. Self-driven, proactive, and results-oriented (“Go-getter attitude”).Good to Have: Experience in advanced nodes (e.g., 7nm/5nm/3nm). Knowledge of multi-domain power intent (UPF). Exposure to cloud-based or distributed PD flows.Education: Bachelor’s or Master’s degree inElectronics / Electrical / VLSI / Computer Engineeringor related field.



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