SmartSoc Solutions

Company Description :

SmartSoC Solutions is a leading Product Engineering company with specialization in Semiconductor, Embedded, Artificial Intelligence, and Automotive domains. We enable our clients to design and build next-generation products, with a focus on Innovation.

Our expertise is in SOC Design & Verification, Physical Design & Verification, Design for Test DFT), FPGA Design & Emulation, Analog Design & Layout, Artificial Intelligence, Data Science, Machine Learning, Deep Learning, Data Analytics, IoT, M2M, ATMP services, Product Engineering, Digital Solutions (Web, Mobile, Cloud, Custom Applications), Infrastructure Management, Network and Cyber Security.

Job description :

Hands On Experience, in IP/SOC Verification Have Experience of one or more Project Cycles including Tape Outs Design & Verification Failure Debugging Skills Verilog, System Verilog, & UVM Testbench Coding Functional Coverage Development, & Coverage Closure Assertion/Checker Development Testcase Planning & Development Practical Knowledge of Protocols like: PCIe, Ethernet, CXL, USB, CAN, LIN, FlexRay, AXI, AHB, APB Concepts in Digital Design Problem Solving & Analytical Skills

Our Reach :

- Operating in 8 countries.

- Partnering with 55 clients.

- Empowering over 1,250 professionals.

Position Details :

- Location : Bangalore and Hyderabad.

- Experience : 4 to 15 years.

- Employment Type : On-site.

Job Requirements :

We are currently seeking talented and experienced Design Verification Engineers to join our team in Bangalore.

As a Design Verification Engineer, you will be responsible for ensuring the functionality, performance, and reliability of our complex designs, with a focus on Core Data Path (CDP), Graphics Data Path (GDP), USB4 (USB 4.0), Power Gating (PG), and Power Management (PM) domains.

We are looking for candidates with 4 to 7+ years of relevant experience in design verification.

Key Responsibilities :

- Verification Planning : Collaborate with design and architecture teams to develop comprehensive verification plans for CDP, GDP, USB4, PG, and PM components.

- Testbench Development : Create and maintain advanced testbenches, including constrained-random and assertion-based methodologies, to thoroughly verify design functionality.

- Functional and Coverage Testing : Execute functional tests and track coverage metrics to ensure exhaustive testing of design features.

- Protocol Verification : Verify compliance with industry-standard protocols, including USB4, and identify and address protocol violations.

- Bug Reporting and Debugging: Document and report issues, and work closely with design teams to resolve bugs in a timely manner.

- Performance Verification : Assess and verify the performance of data path components, ensuring they meet specified requirements.

- Power Verification : Verify power management and power gating strategies to optimize power consumption.

- Scripting and Automation : Develop and use scripting languages and automation tools to streamline verification processes.

- Documentation : Prepare detailed verification plans, test reports, and documentation cation and teamwork skills.

Position Requirements :

- Minimum B.E./ B.Tech degree in Electrical/Electronics/Computer science

- 4 - 15 years experience in design verification with UVM and constrained random, coverage-based verification approaches

- Strong understanding of DV concepts with an eye on developing scalable DV environment architecture that realizes first pass DV success

- Experience with translating Design Verification (DV) requirements such as test plans into a robust DV environment and generate coverage metrics for demonstrating DV convergence

- Adaptability to learn end application/systems and map into smart verification test plans

Excellent debugging and analytical skills

- Good interpersonal, teamwork and communication skills to logically & effectively drive discussions with teams spread geographically

- Knowledge of Assertion based formal verification

- Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus

- Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus

- Experience with ASIC/ SoC product DV & productization is very desirable has context menu