IP Verification Engineer

3 days ago


Bengaluru, India Leadsoc Full time

Job Title : DV IP/Subsystem level.

Experience : 8 Years+.

Location : Bangalore/Hyderabad.

- Coding hands on SV/UVM.

- Can work independently on tasks such code UVM/SV based -components/relevant logic, testcase development.

- Can debug test failures and root cause issue independently in complex design.

- Have exposure to PCIe and AXI.

- Good reasoning and communication skills.

Role Description :


As a DV IP/Subsystem Level Engineer, you will play a crucial role in ensuring the quality and reliability of complex digital IC designs.


- You will be responsible for developing and executing comprehensive verification testbenches to validate the functionality and performance of IP blocks and subsystems.


Key Responsibilities :


Testbench Development :


- Develop and maintain high-quality UVM-based testbenches for IP blocks and subsystems.


Testcase Development :


- Create comprehensive testcases to cover all functional and performance aspects of the design.


Verification Execution :


- Execute regression tests and debug test failures.


Root Cause Analysis :


- Analyze test failures to identify root causes and propose solutions.


Coverage Driven Verification :


- Utilize coverage-driven verification techniques to ensure adequate test :


- Collaborate with design and verification teams to ensure efficient and effective verification.


Qualifications :


Technical Skills :


- Strong proficiency in Verilog/System Verilog and UVM methodologies


- Experience in developing complex testbenches and testcases


- Knowledge of digital design principles and verification concepts


- Familiarity with industry-standard verification tools (e.g., QuestaSim, VCS)


- Exposure to PCIe and AXI protocols

(ref:hirist.tech)

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