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ASIC Verification Engineer
3 months ago
Role : ASIC (SOC) Design Verification
Exp : 4 to 15 Years
Job Location : Bangalore, Chennai, Noida, Ahmedabad, Pune, Hyderabad (For Hyderabad We need 5+ Years experience, Other Locations 4+ Years of Experience)
Role :
- Hands on experience in SOC/Sub System/block level functional verification using System Verilog/UVM.
- Strong knowledge of UVM, advance UVM,System Verilog.
- Must have worked on development of testplan, testbench components, verification environment, interface agents, Scoreboard in UVM.
- Understanding of complete functional verification cycle will be added advantage
- Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB, AMBA or similar is required.
- Skills to debug RTL & testbench issues, test failures.
- Experience on verification closure by closing Coverage and bug reports
- Primarily knowledge of Script development and maintenance
- Understanding of customer dynamic environment change and adopt run time changes in schedule, design etc
(ref:hirist.tech)
