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Physical Design Engineer
3 months ago
The Radar and Analytics group at Texas Instruments India is looking for passionate Physical Design Engineer to work on next-gen CMOS single-chip millimeter wave sensor portfolio for Automotive Radar and Industrial applications.
Physical Design team here owns Complete So C Synthesis to Layout closure including constraints development and STA & is responsible for design handoff to manufacturing.
Physical Design team at Radar & Analytics also works closely with systems and designs team for PPA optimization and has good knowledge of system aspects of the device usage.
About the Group:
The Radar and Analytics team has delivered world's most precise millimeter wave sensor available today on a single chip.
This team has come-up with World's first CMOS based mm Wave Radar sensor.
It integrates a high-performance radar RF front end with best-in-class DSP and MCU to achieve a wide portfolio of single chip, high-performance, low-power mm Wave Radar sensors catering to automotive and industrial markets.
The applications range from ultra-short and short range to front long range radar, proximity sensing, level sensing, traffic monitoring, drone and many more.
With accuracy up to 3x that of competing solutions, TI's mm Wave radar sensors provide the crucial range, velocity and angle measurements essential to these applications.
Here are some of the recent acknowledgements for our First-gen millimeter wave radar sensors:CES 2018 Innovation Award Honoree in three categories
Electronic Products 2017 Product of the Year in the Sensing Category
2017 Annual Creativity in Electronics (ACE) Award for Sensor of the Year
Do you want to know more about us? - Check out
Who are we and what do we do?
Part of the Embedded Processing (EP) business, the Radar and Analytics (RAP) design team develops highly integrated system-on-chips (So Cs) with DSP, MCUs and an RF front-end for industrial and automotive applications.
The team has been responsible for architecting and developing So Cs with differentiated IPs, digital front-end, complex hardware accelerators, safety and security infrastructure and multiple digital subsystems with a track record of first pass silicon success.
The team's next charter involves development and implementation of top-notch second and third generation Radar sensor So Cs that will exceed the benchmark set by the team in terms of the quality and flawless execution of its first generation radar sensor devices (XWR1242, XWR1443, XWR1642) , enabling TI to broaden its portfolio of mm Wave sensors.
What will you be doing in this role? (Responsibilities)
As a Physical Design Engineer in the team, you will be working independently on the entire flow from RTL to GDSII.
Responsible for Place & Route, Reliability and Physical verification, Reliability closure
Methodologies to keep the PD cycle efficient and predictable.
Techniques to reduce Power and Area to make the device competitive
Techniques used in automotive designs.
Ability to interface with Fab and Qualification teams.
What do we expect from you? (Minimum Qualifications)
Bachelor or Master's degree in Electrical/Electronics Engineering.
1-2 years of Industry experience
Understanding of DFT architectures
Good understanding and mastery in PD flow using Cadence tools and basic TCL scripting.
Knowledge of design requirements and guidelines for automotive applications and associated analog DFT hooks is a desirable
High speed (up to 2 Ghz) design closure experience
Experience/Understanding of Backend flows like Synthesis, Floorplan & Powerplan, Placement, Clock Tree Synthesis, Route, STA, Reliability & Physical verification closure.
Preferred Skills/ ExperienceExperienced with IC design and full development cycle from definition through release to production.
Effective communication skills to interact with all stakeholders.
Team and People Skills:
The candidate should have good people skills to work closely with the systems, analog, layout and test team
Must be highly focused and remain committed to obtaining closure on project goals
