Shared Cache Verification Engineer

2 weeks ago

Bengaluru, India Tenstorrent Full time

The Tenstorrent team combines technologists from different disciplines who come together with a shared passion for AI and a deep desire to build great products. We value collaboration, curiosity, and a commitment to solving hard problems. Find out more about our culture.


Shared Cache Verification Engineer:


Experienced engineer focused on L2/Shared Cache verification for high-performance CPUs. The person coming into this role will work on a server class L2/Shared Cache unit

Responsibilities

  • Functional and performance verification of the L2/Shared Cache unit for a from-scratch high performance CPU while working closely with Architecture and RTL team
  • Develop detailed block level verification plans for L2/Shared Cache that includes both architectural (RISCV ISA) and microarchitectural functionality
  • Design and develop reusable block level testbench components in SV, UVM and C++, that include microarchitectural models, monitors, checkers
  • Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
  • Evaluate and integrate open-source toolchains into the DV flow
  • Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
  • Work with design, test and post silicon validation teams to ensure high quality delivery of the L2/Shared Cache block

Experience & Qualifications

  • BS/MS/PhD in EE/ECE/CE/CS with at least 7 years of experience
  • Strong background and experience with high performance OOO CPU microarchitecture especially with load/store, caches and memory subsystem
  • Experience working on an x86, ARM or RISCV based CPU is desirable
  • Architectural understanding of address translation, memory ordering, cache coherence protocols, memory consistency, multi-processors and fabric topologies
  • Significant experience debugging RTL and DV in a simulation environment
  • Verification methodologies and techniques – Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools
  • Experience with C++ / SV / UVM as well as scripting languages
  • Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
  • Strong problem solving and debug skills across various levels of design hierarchies

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